Embodiments of the present disclosure may relate to integrated circuit devices, control signal generation circuits, semiconductor modules, and semiconductor systems including the same.
Within semiconductor systems, it is generally necessary to match the impedance of a transmission line (e.g., a transmission channel) with the corresponding termination impedance (e.g., a termination resistor) in order to prevent undesirable signal reflections. Such signal reflections act as noise on the signal line in relation to signals subsequently transmitted on the transmission line. The termination resistors of the conventional semiconductor modules or systems have been disposed outside semiconductor chips constituting the semiconductor modules or systems. However, in the event that the termination resistors are disposed outside high performance semiconductor chips such as double data rate 2(DDR2) synchronous dynamic random access memory (SDRAM) chips, there may be some limitations in preventing the undesirable signal reflections.
Recently, the termination resistors have been disposed inside the high performance semiconductor chips to prevent the undesirable signal reflections. That is, on-die termination (ODT) circuits have been widely used in the semiconductor modules and/or the semiconductor systems. In general, the ODT circuit may be enabled to operate when an ODT signal having a logic high voltage level is applied to an ODT pad of the semiconductor chip. Also, the ODT circuit may be disabled not to operate when an ODT signal having a logic high voltage level is applied to the ODT pad of the semiconductor chip.
A pair of semiconductor chips may be packaged to realize a semiconductor module, and the semiconductor module may employ a dual rank configuration so that the pair of semiconductor chips of the semiconductor module are controlled by a single shared channel. The single shared channel may include a data channel through which data is inputted and/or outputted and an address/command channel through which an address signal and command signal is inputted and/or outputted.
In the semiconductor module employing the dual rank configuration, each of the semiconductor chips may include the ODT circuit. Thus, two ODT signals may be required to independently operate the ODT circuits included in the semiconductor chips, and the semiconductor module should be configured to include pins for receiving the ODT signals. If the number of the pins of the semiconductor module increases, manufacturing costs of the semiconductor module may also increase. Accordingly, in the conventional semiconductor module including two semiconductor chips, the ODT circuit of one of the semiconductor chips may be disabled and both the semiconductor chips may share the ODT circuit of the other semiconductor chip. As a result, the manufacturing costs of the semiconductor module can be reduced since only one pin is required to receive the ODT signal.
Meanwhile, in the conventional semiconductor module employing the dual rank configuration, the semiconductor chip having the disabled ODT circuit may not have any available ODT circuits when the semiconductor chip having the shared ODT circuit is in a power down mode. That is, when the semiconductor chip having the shared ODT circuit is in the power down mode, the shared ODT circuit may be disabled. Accordingly, if the semiconductor chip having the shared ODT circuit is in the power down mode, the shared ODT circuit may not be activated even though the semiconductor chip having the disabled ODT circuit executes a write operation.